As is well known, EEPROM memory structured, while being non-volatile types, allow the information contained therein to be modified electrically at both the write and the erase phases of their operation. Furthermore, they distinguish themselves by the kind of their electric programming, which may take place in either the "page" mode or the "byte" mode.
In the former mode, all the cells in one row of the matrix are addressed at one time. In the latter mode, one byte only is addressed of the several available in one row.
It is also known that the state of any cell in the EEPROM memory can be altered by means of electron flow passing by tunnel effect through a thin layer of silicon oxide associated with the floating gate of the cell. The thin oxide region occupies a smaller area than the floating gate, where the electric charge is stored.
There exist different types of EEPROM memory cells which are identifiable by the number of their polysilicon layers.
In fact, there are cells with single, double, or triple layers of polysilicon. Most commonly employed are cells with two-level of polysilicon, known as FLOTOX cells Such cells are described, for instance, in an article "Oxide reliability criterion for the evaluation of endurance performance of electrically erasable programmable read-only memories", Journal App. Phys., 71, No. 9, 1992.
Irrespective of the number of the polysilicon layers, for the write and erase phases of the cells, it is common practice to use positive voltages, applied to the diffusion underlying the tunnel region or the control gate. Such voltages vary between 8 and 18 volts, in order to generate across the thin oxide an electric field which is sufficiently strong to positively trigger the tunnel effect.
However, the use of such comparatively high positive voltages may result over time in the thin oxide layer being deteriorated, thereby damaging the cells and the whole memory structure beyond repair.
One might think of obviating this problem by using negative voltages for programming, e.g., during the writing phase.
However, with conventional type cells, byte mode programming is carried out by splitting the control gate into segments which are common to a single byte (e.g., eight or sixteen bits). The control gate is then selected by means of a column decoder external of the cells matrix, and is enabled by a select transistor shared by all the cells in one row. In this way, the programming will only be enabled in the selected byte.
But the use of a negative voltage during this programming phase may create some serious problems. As an example, a large integrated circuit area would have to be used for selecting a single byte, because each segment of the control gate requires the arrangement of a switch adapted to handle both the positive voltages and the negative voltages applied during the programming phase.